PowerPC Platform - definition. What is PowerPC Platform
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%ما هو (من)٪ 1 - تعريف

RISC INSTRUCTION SET ARCHITECTURE BY AIM ALLIANCE
PowerPC chip; PowerPC family; PowerPC Endian Modes; Powerpc; PowerPC processor; Powerpc processor; Power PC; PowerPC Platform; Power pc; PPC32; Power Performance Computing; IBM PPC; IBM PowerPC; Performance Optimization With Enhanced RISC – Performance Computing; Performance Optimization With Enhanced RISC - Performance Computing; Macppc; Embedded PowerPC Operating System; PowerPC 2.02; PowerPC 2.0; PowerPC 2.01
  • PowerPC 604e]] 200 MHz
  • IBM PowerPC 601 microprocessor
  • ISAs]]
  • The Freescale XPC855T Service Processor of a [[Sun Fire]] V20z

PowerPC Platform         
<architecture, standard> (PPCP, PReP - PowerPC Reference Platform, formerly CHRP - Common Hardware Reference Platform) An open system standard, designed by IBM, intended to ensure compatibility among PowerPC-based systems built by different companies. The PReP standard specifies the PCI bus, but will also support ISA, MicroChannel and PCMCIA. PReP-compliant systems will be able to run the Macintosh OS, OS/2, WorkplaceOS, AIX, Solaris, Taligent and Windows NT. IBM systems will (of course) be PReP-compliant. Apple's first PowerPC Macintoshes will not be compliant, but future ones may be. {IBM info (http://fnctsrv0.chips.ibm.com/products/ppc/L3ppcp.html)}. http://billboard.emedia.com.au/chipster/computers/CHRP/whatsCHRP.html. [Current OS statuses?] (1997-03-23)
PowerPC         
<processor, standard> (PPC) A RISC microprocessor designed to meet a standard which was jointly designed by Motorola, IBM, and Apple Computer (the PowerPC Alliance). The PowerPC standard specifies a common {instruction set architecture} (ISA), allowing anyone to design and fabricate PowerPC processors, which will run the same code. The PowerPC architecture is based on the IBM POWER architecture, used in IBM's RS/6000 workstations. Currently IBM and Motorola are working on PowerPC chips. The PowerPC standard specifies both 32-bit and 64-bit data paths. Early implementations were 32-bit (e.g. {PowerPC 601}); later higher-performance implementations were 64-bit (e.g. PowerPC 620). A PowerPC has 32 integer registers (32- or 64 bit) and 32 floating-point (IEEE standard 64 bit) floating-point registers. The POWER CPU chip and PowerPC have a (large) common core, but both have instructions that the other doesn't. The PowerPC offers the following features that POWER does not: Support for running in little-endian mode. Addition of single precision floating-point operations. Control of branch prediction direction. A hardware coherency model (not in Book I). Some other floating-point instructions (some optional). The real time clock (upper and lower) was replaced with the time base registers (upper and lower), which don't count in sec/ns (the decrementer also changed). 64-bit instruction operands, registers, etc. (in 64 bit processors). See also PowerOpen, PowerPC Platform (PReP). {IBM PPC info (http://fnctsrv0.chips.ibm.com/products/ppc/index.html)}. gopher://info.hed.apple.com/, "Apple Corporate News/" (press releases), "Apple Technologies/" and "Product Information/". gopher://ike.engr.washington.edu/, "IBM General News/", "IBM Product Announcements/", "IBM Detailed Product Announcements/", "IBM Hardware Catalog/". Usenet newsgroups: news:comp.sys.powerpc, news:comp.sys.mac.hardware. ["Microprocessor Report", 16 October 1991]. (1994-09-30)
PowerPC 600         
  • An IBM manufactured 90 MHz PowerPC 601v. Notice the slightly smaller die.
  • IBM PPC603ev, 200 MHz
MICROARCHITECTURE
PowerPC 604e; 604e; PowerPC 601; PowerPC 604; PowerPC 603; PowerPC 620; PowerPC 603e; PowerPC 603ev; 60x; PowerPC G2; PowerPC 601v; PowerPC 604ev; PowerPC 603q; PowerPC G1; Power PC 604e
The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance.

ويكيبيديا

PowerPC

PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.

PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform (CHRP) initiatives in the 1990s. Originally intended for personal computers, the architecture is well known for being used by Apple's Power Macintosh, PowerBook, iMac, iBook, eMac, Mac Mini, and Xserve lines from 1994 until 2005, when Apple migrated to Intel's x86. It has since become a niche in personal computers, but remains popular for embedded and high-performance processors. Its use in the 7th generation of video game consoles and embedded applications provide an array of uses, including satellites, and the Curiosity and Perseverance rovers on Mars. In addition, PowerPC CPUs are still used in AmigaOne and third party AmigaOS 4 personal computers.

PowerPC is largely based on the earlier IBM POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the Power series use the Power ISA.